1. Field of the Invention
The present invention relates to architectures for network interface controllers, and particularly to architectures for managing the transmission and reception of data between a host system and a network.
2. Description of Related Art
Network interface controllers are involved in the management of the transfer of data between a host computer system and a communications network which is typically asynchronous and independent of the host system. Thus, data may be received across the network at times when the host is unable to process the received information directly. Similarly, when the host desires to transmit information on the network, the flow of data from the host system to the network must be managed. Prior art network interface controllers manage this asynchronous interface with the use of buffers in host managed memory. Received data is typically supplied from a media access controller (MAC) through a FIFO buffer on a network interface controller card into a host managed receive area buffer, either in the host address space or in adapter memory that is managed by the host, using DMA techniques that relieve the host processor from many of the sequential addressing tasks involved in uploading the data from the network into the receive area buffers. When the host desires to utilize or review the information received, h reads from the host receive area buffers, and transfers information out of the receive area buffers to permanent locations for use by the host system.
Similarly, when the host system transmits data, in prior art systems, it typically writes the data into a host managed transmit buffer area, and the network interface controller transfers that data from the host managed space using DMA techniques through a FIFO buffer in the interface controller and on to the network through a MAC.
Various devices have been developed which tend to optimize the DMA techniques used for managing the flow of data between the host system address space and the network interface controller. Representative prior art systems include the National Semiconductor DP83932B, a Systems-Oriented Network Interface Controller (SONIC) and the Intel 82586 Local Area Network Coprocessor. However, these prior art systems rely on host system address space for the receive and transmit buffers, and utilize a significant portion of the host processor overhead and host bus bandwidth.
It is desirable to provide a network interface controller which minimizes the use of host processor overhead and host system bus bandwidth, and simplifies the software executed by the host required for managing the interface.